A multiple-port memory cell, such as a two port memory cell or a dual-port memory cell, includes at least a first access port and a second access port both configured for individually accessing a data node of the memory cell. A memory macro of multiple-port memory cells includes a plurality of multiple-port memory cells and is capable of accessing two or more of its memory cells during a single clock cycle using different word line signals associated with different access ports. In some applications, various word lines carry the word line signals, and the word lines extend in parallel over the memory cells. A signal transition on any one of the word lines would interfere with a word line signal on another one of the word lines through capacitive coupling.